SetCtrlSpr(ISASI)

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Sets specific bits of the CTRL register (control register).

Prototype

template <int8_t startBit, int8_t endBit>
__aicore__ static inline void SetCtrlSpr(int64_t value)

Parameters

**Table 1** Template parameters
Parameter	Description
startBit	Start bit index.
endBit	End bit index.

**Table 2** Parameters
Parameter	Input/Output	Description
value	Input	New value set for the start and end bits.

**Table 3** Common CTRL register bits
CTRL Register Bit	Function	Default Value	Related API
CTRL[8:6]	Controls the enabling of atomic operations and data type selection when data is moved from L0C Buffer, Unified Buffer, or L1 Buffer to the global memory. 3'b000: Atomic operations are disabled. 3'b001: Atomic operations are enabled, and the data type is float. 3'b010: Atomic operations are enabled, and the data type is half. 3'b011: Atomic operations are enabled, and the data type is int16_t. 3'b100: Atomic operations are enabled, and the data type is int32_t. 3'b101: Atomic operations are enabled, and the data type is int8_t. 3'b110: Atomic operations are enabled, and the data type is bfloat16_t.	3'b000	N/A
CTRL[10:9]	Controls the atomic operation type. This control bit is valid only when atomic operations are enabled via CTRL[8:6]. 2'b00: ADD 2'b01: MAX 2'b10: MIN	2'b00	N/A
CTRL[45]	Controls the data type when data from the left and right matrices is used for MMAD computation. 1'b0: The original data type is used. 1'b1: When data from the left and right matrices are both of the fp8_e4m3fn_t type, the data is considered as the hifloat8_t type for matrix multiplication. In other scenarios, the original data type is used.	1'b0	N/A
CTRL[48]	Controls the saturation mode during float computation and precision conversion. This control bit is valid only when CTRL[60] is enabled. 1'b0: saturation mode. The INF output is saturated to ±MAX, and the NaN output is saturated to 0. 1'b1: non-saturation mode. The INF/NAN output remains unchanged. This control bit supports only the following data types: half for float computation Data types for float precision conversion: hifloat8_t, fp8_e8m0_t, fp8_e5m2_t, fp8_e4m3fn_t, half, and bfloat16_t	1'b0	Related APIs: Vector computation API Atomic operation API Precision conversion instruction API Constraints: The data type constraints must be met. During atomic operations, if this control bit needs to be reconfigured, call DataCacheCleanAndInvalid to clear the current cache line status and write out the current data to prevent the saturation mode change from affecting the current data. For details about the calling example, see the example of configuring the global non-saturation mode for the half type in atomic operations.
CTRL[50]	Controls the NAN saturation mode during float precision conversion. This control bit is valid only when CTRL[48] is set to the saturation mode. 1'b0: The NAN output is converted to 0.0. 1'b1: The NAN output remains NAN. This control bit supports only the following data types: fp8_e8m0_t, fp8_e5m2_t, and fp8_e4m3fn_t	1'b0	Precision conversion instruction API (The data type constraints must be met.)
CTRL[53]	Controls the saturation mode of integer computation instructions. 1'b0: truncation mode. The overflow value is truncated based on the number of bits of the target data type, with the lower bits retained and the upper bits discarded. 1'b1: saturation mode. The overflow value is saturated to ±MAX.	1'b0	Vector computation API (The input and output data are both of the integer type.)
CTRL[59]	Controls the saturation mode for float-to-integer or integer-to-integer precision conversion. This control bit is valid only when CTRL[60] is enabled. 1'b0: saturation mode. The overflow value is saturated to ±MAX. 1'b1: truncation mode. The overflow value is truncated based on the number of bits of the target data type, with the lower bits retained and the upper bits discarded.	1'b0	Precision conversion instruction API
CTRL[60]	Controls the global effective mode of the saturation mode. 1'b0: single-instruction saturation 1'b1: global saturation	1'b1	This control bit can be used together with the Reg vector computation API Cast or with CTRL[48] and CTRL[59]. For details about the configuration, see Table 4.

**Table 4** Global or single-instruction saturation
Global Enable Bit	Control Bit	Function
CTRL[60] = 1'b0	In the trait template parameter of the Reg vector computation API Cast, set satMode to SatMode::NO_SAT.	Single-instruction non-saturation mode
CTRL[60] = 1'b0	In the trait template parameter of the Reg vector computation API Cast, set satMode to SatMode::SAT.	Single-instruction saturation mode
CTRL[60] = 1'b1	CTRL[48] = 1'b1	Global non-saturation mode (float computation and float precision conversion)
	CTRL[48] = 1'b0	Global saturation mode (float computation and float precision conversion)
	CTRL[59] = 1'b1	Global non-saturation mode (float-to-integer or integer-to-integer precision conversion)
	CTRL[59] = 1'b0	Global saturation mode (float-to-integer or integer-to-integer precision conversion)

Returns

None

Constraints

Only the CTRL[8:6], CTRL[10:9], CTRL[45], CTRL[48], CTRL[50], CTRL[53], CTRL[59], and CTRL[60] bits are supported.
Atomic operation APIs have been encapsulated for setting CTRL[8:6] and CTRL[10:9]. You are advised to use these APIs.

Examples

In the following example, the atomic operation mode is enabled and the data type is float.
```
AscendC::SetCtrlSpr<6, 8>(1);
```

Example of configuring the global non-saturation mode for the half type in atomic operations:

AscendC::SetCtrlSpr<6, 8>(2);
AscendC::SetAtomicAdd<half>();
AscendC::DataCacheCleanAndInvalid<half, AscendC::CacheLine::ENTIRE_DATA_CACHE, AscendC::DcciDst::CACHELINE_ATOMIC>(dstTensor);
AscendC::SetCtrlSpr<48, 48>(1);
...

Parent topic: TPosition