Memory Access
Transferring a Large Data Block at a Time
Using 512-Byte Alignment for the GM Address
Using the Data Transfer API Efficiently
Reducing Invalid Data Transfers in Non-Alignment Scenarios
Reducing the Number of Transfers in Non-contiguous Transfer Scenarios
Avoiding Same-Address Access
Setting a Proper L2 CacheMode
Using Shared Temporary Buffer for Operators and High-Level APIs
Reusing VECIN and VECOUT for Transfer Operators
Reducing the Tensor ShapeInfo Dimensions to Optimize the Stack Space
Avoiding Bank Conflicts in the Unified Buffer
L2 Cache Tiling
Parent topic:
SIMD Operator Performance Optimization