[Priority] High

[Overview]

To improve data access efficiency and throughput, the Unified Buffer uses a memory module (bank) structure with equal sizes. When multiple read and write instructions access the Unified Buffer at the same time, these instructions cannot be executed simultaneously due to hardware resource limitations, resulting in bank conflicts. In this case, instructions need to queue for resources and cannot be completed within one instruction cycle.

For NPU architecture version 220x

The total size of the UB is 192 KB, including 16 bank groups. Each bank group contains three banks. Each bank is 4 KB in size and consists of 128 rows, with each row being 32 bytes long.
- Read/Write conflict: A read operation and a write operation attempt to access the same bank at the same time.
- Write/Write conflict: Multiple write operations attempt to access the same bank group at the same time.
- Read/Read conflict: Multiple read operations attempt to access the same bank group at the same time.
For Atlas 350 Accelerator Card:

The total size of the UB is 256 KB, which contains eight bank groups. Each bank group contains two banks. Each bank is 16 KB in size and consists of 512 rows, with each row being 32 bytes long.
- Read/Write conflict: A read operation and a write operation attempt to access the same bank at the same time.
- Write/Write conflict: Multiple write operations attempt to access the same bank group at the same time.
- Read/Read conflict: Two read operations attempt to access the same bank at the same time, or two or more read operations attempt to access the same bank group at the same time.

It can be seen that the bank conflict scenario is closely related to the specifications of the Unified Buffer. Changes in the specifications usually lead to changes in the bank conflict scenario.

Because the bank group of the Atlas 350 Accelerator Card has two groups of read and write ports, no conflict occurs when two read operations access different banks in the same bank group.
Assume that the address of the read instruction operation is 0x0000 (bank0) and the address of the write instruction operation is 0x10000. In the NPU architecture version 220x, no read/write conflict occurs at address 0x10000 (bank16). However, in the Atlas 350 Accelerator Card architecture, a read/write conflict occurs at address 0x10000 (bank0).

The following describes how to avoid bank conflicts in different hardware architectures.